A display device equipped with a semiconductor element having a plurality of terminals is known as a conventional technology. FIG. 12 is a plan view showing a configuration of a display device equipped with a semiconductor element of a conventional example. FIG. 13 is a plan view showing a configuration of a semiconductor element of the conventional example shown in FIG. 12. FIG. 14 is a plan view showing a configuration of a display panel of the display device of the conventional example shown in FIG. 12. FIG. 15 is a cross-sectional view of the semiconductor element of the conventional example shown in FIG. 12 as it is mounted on the display panel.
As shown in FIG. 12, a display device 501 equipped with a semiconductor element 510 of a conventional example includes a semiconductor element 510 and a display panel 520 with the semiconductor element 510 mounted thereon. As shown in FIG. 13, the semiconductor element 510 includes a main surface 511 of a rectangular shape having two long sides 511a and 511b and two short sides 511c and 511d. On the main surface 511, a plurality of output bumps 512 and a plurality of input bumps 513 are provided and are aligned in the direction (direction A) along the long sides 511a and 511b, respectively.
The plurality of output bumps 512 are arranged close to the long side 511a, while the plurality of input bumps 513 are arranged close to the long side 511b. The plurality of output bumps 512 are arranged to form two rows of terminals. Also, the plurality of output bumps 512 are arranged in a staggered fashion. The plurality of input bumps 513 are arranged to form a row of terminals.
The plurality of output bumps 512 are arranged in the direction A at a pitch of 16 μm, for example. Also, the plurality of output bumps 512 include a plurality of (hundreds of) source bumps 512a that are arranged about the center of the long side 511a and also a plurality of (hundreds of) gate bumps 512b that are arranged towards the ends of the long side 511a. The plurality of source bumps 512a constitute a source output section 512c, and the plurality of gate bumps 512b constitute a gate output section 512d. 
As shown in FIG. 12, the display panel 520 includes a display section 521 and also a margin section 522 that is formed along an edge of the display panel 520. In the margin section 522, a mounting area 522a is provided for the semiconductor element 510 to be mounted thereon.
In the mounting area 522a, as shown in FIG. 14, a plurality of pads 523 are formed at positions corresponding to the plurality of output bumps 512 of the semiconductor element 510 (see FIG. 13). Also, pads (not shown) are formed at positions corresponding to the plurality of input bumps 513 of the semiconductor element 510 (see FIG. 13).
The pads 523 include a plurality of source pads 523a that are arranged at positions corresponding to the plurality of source bumps 512a (see FIG. 13) and also a plurality of gate pads 523b that are arranged at positions corresponding to the plurality of gate bumps 512b (see FIG. 13). The plurality of source pads 523a constitute a source section 523c, while the plurality of gate pads 523b constitute a gate section 523d. 
A plurality of wirings 524, which are formed so as to extend to the display section 521 (see FIG. 12), are connected to the source pads 523a and the gate pads 523b. The source pads 523a are connected to one side of the display section 521 in the direction B through the wirings 524, while the gate pads 523b are connected to both sides of the display section 521 in the direction A through the wirings 524.
In the display device 501 of the conventional example, when mounting the semiconductor element 510 to the display panel 520, the semiconductor element 510 is bonded to the display panel 520 by thermocompression with an ACF (anisotropic conductive film; not shown) or the like sandwiched between the output bumps 512 and input bumps 513 of the semiconductor element 510 and the pads 523 and pads (not shown) of the display panel 520.
The above-described display device is disclosed in literatures such as Patent Document 1 and Patent Document 2.